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1 file number 3149.2 hi-539 precision, 4-channel, low-level, differential multiplexer the intersil hi-539 is a monolithic, 4-channel, differential multiplexer. two digital inputs are provided for channel selection, plus an enable input to disconnect all channels. performance is guaranteed for each channel over the voltage range 10v, but is optimized for low level differential signals. leakage current, for example, which varies slightly with input voltage, has its distribution centered at zero input volts. in most monolithic multiplexers, the net differential offset due to thermal effects becomes signi?cant for low level signals. this problem is minimized in the hi-539 by symmetrical placement of critical circuitry with respect to the few heat producing devices. supply voltages are 15v and power consumption is only 2.5mw. features ? differential performance, typical: -low d r on , 125 o c . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 w -low d i d(on) , 125 o c . . . . . . . . . . . . . . . . . . . . . . . 0.6na -low d charge injection . . . . . . . . . . . . . . . . . . . . 0.1pc - low crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . -124db ? settling time, 0.01% . . . . . . . . . . . . . . . . . . . . . . . 900ns ? wide supply range . . . . . . . . . . . . . . . . . . . 5v to 18v ? break-before-make switching ? no latch-up applications ? low level data acquisition ? precision instrumentation ? test systems ordering information part number temp. range ( o c) package pkg. no. hi1-0539-5 0 to 75 16 ld cerdip f16.3 hi1-0539-8 -55 to 125 16 ld cerdip f16.3 HI3-0539-5 0 to 75 16 ld pdip e16.3 hi4p0539-5 0 to 75 20 ld plcc n20.35 truth table en a 1 a 0 on channel to out a out b l x x none none hll1a1b hlh2a2b hhl3a3b h h h 4a 4b pinouts hi-539 (cerdip, pdip) top view hi-539 (plcc) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 0 en v- in 1a in 2a in 3a out a in 4a a 1 v+ in 1b in 2b in 3b in 4b out b gnd 19 3 2 20 1 15 16 17 18 14 9 10 11 12 13 4 5 6 7 8 in 1a nc in 2a in 3a v- in 4a out a nc out b in 4b in 1b nc in 2b in 3b v+ en a 0 nc a 1 gnd data sheet july 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
2 absolute maximum ratings thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40v v+ or v- to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v analog signal (v in , v out ). . . . . . . . . . . . . . . . . . . . . . . . . . v- to v+ digital input voltage (v en , v a ) . . . . . . . . . . . . . . . . . . . . . . v- to v+ analog current (in or out) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma operating conditions temperature range hi-539-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c hi-539-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 85 32 pdip package . . . . . . . . . . . . . . . . . . . 90 n/a plcc package. . . . . . . . . . . . . . . . . . . 80 n/a maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (plcc - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations supplies = 15v, v en = 4v, v ah (logic level high) = 4v, v al (logic level low) = 0.8v, unless otherwise speci?ed parameter test conditions temp ( o c) -8 -5 units min typ max min typ max dynamic characteristics access time, t a 25 - 250 750 - 250 750 ns full - - 1,000 - - 1,000 ns break-before-make delay, t open 25 30 85 - 30 85 - ns full 30 - - 30 - - ns enable delay (on), t on(en) 25 - 250 750 - 250 750 ns full - - 1,000 - - 1,000 ns enable delay (off), t off(en) 25 - 160 650 - 160 650 ns full - - 900 - - 900 ns settling time to 0.01% 25 - 0.9 - - 0.9 - m s charge injection (output) full - 3 - - 3 - pc d charge injection (output) full - 0.1 - - 0.1 - pc charge injection (input) full - 10 - - 10 - pc differential crosstalk note 4 25 - -124 - - -124 - db single ended crosstalk note 4 25 - -100 - - -100 - db channel input capacitance, c s(off) full - 5 - - 5 - pf channel output capacitance, c d(off) full - 7 - - 7 - pf channel on output capacitance, c d(on) full - 17 - - 17 - pf input to output capacitance, c ds(off) note 5 full - 0.08 - - 0.08 - pf digital input capacitance, c a full - 3 - - 3 - pf digital input characteristics input low threshold, v al full - - 0.8 - - 0.8 v input high threshold, v ah full 4.0 - - 4.0 - - v input leakage current (high), i ah full - - 1 - - 1 m a input leakage current (low), i al full - - 1 - - 1 m a hi-539
3 analog channel characteristics analog signal range, v in full -10 - +10 -10 - +10 v on resistance, r on v in = 0v 25 - 650 850 - 650 850 w full - 950 1.3k - 800 1k w v ln = 10v 25 - 700 900 - 700 900 w full - 1.1k 1.4k - 900 1.1k w d r on, (side a-side b) v in = 0v 25 - 4.0 24 - 4.0 24 w full - 4.75 28 - 4.0 24 w v ln = 10v 25 - 4.5 27 - 4.5 27 w full - 5.5 33 - 4.5 27 w off input leakage current, i s(off) condition 0v (note 2) 25 -30- -30-pa full - 2 10 - 0.2 1 na condition 10v (note 2) 25 - 100 - - 100 - pa full - 5 25 - 0.5 2.5 na d i s(off), (side a-side b) condition 0v 25 - 3 - - 3 - pa full - 0.2 2 - 0.02 0.2 na condition 10v 25 - 10 - - 10 - pa full - 0.5 5 - 0.05 0.5 na off output leakage current, i d(off) condition 0v (note 2) 25 -30- -30-pa full - 2 10 - 0.2 1 na condition 10v (note 2) 25 - 100 - - 100 - pa full - 5 25 - 0.5 2.5 na d i d(off), (side a-side b) condition 0v 25 - 3 - - 3 - pa full - 0.2 2 - 0.02 0.2 na condition 10v 25 - 10 - - 10 - pa full - 0.5 5 - 0.05 0.5 na on channel leakage current, i d(on) condition 0v (note 2) 25 -50- -50-pa full - 5 25 - 0.5 2.5 na condition 10v (note 2) 25 - 150 - - 150 - pa full - 6 40 - 0.8 4.0 na d i d(on), (side a-side b) condition 0v 25 - 10 - - 10 - pa full - 0.5 5 - 0.05 0.5 na condition 10v 25 - 30 - - 30 - pa full - 0.6 6 - 0.08 0.8 na differential offset voltage, d v os note 3 25 - 0.02 - - 0.02 - m v full - 0.70 - - 0.08 - m v power supply characteristics power dissipation, p d 25 - 2.3 - - 2.3 - mw full - - 45 - - 45 mw current, l+ 25 - 0.150 - - 0.150 - ma full - - 2.0 - - 2.0 ma electrical speci?cations supplies = 15v, v en = 4v, v ah (logic level high) = 4v, v al (logic level low) = 0.8v, unless otherwise speci?ed (continued) parameter test conditions temp ( o c) -8 -5 units min typ max min typ max hi-539
4 current, l- 25 - 0.001 - - 0.001 - ma full - - 1.0 - - 1.0 ma supply voltage range full 5 15 18 5 15 18 v notes: 2. see figures 2b, 2c, 2d. the condition 10v means: l s(off) and i d(off) : (v s = +10v, v d = -10v), then (v s = -10v, v d = +10v) i d(on) : (+10v, then -10v) 3. d v os (exclusive of thermocouple effects) = r on d i d(on) + i d(on) d r on . see applications section for discussion of additional v os error. 4. v ln = 1khz, 15v p-p on all but the selected channel. see figure 7. 5. calculated from typical single-ended crosstalk performance. electrical speci?cations supplies = 15v, v en = 4v, v ah (logic level high) = 4v, v al (logic level low) = 0.8v, unless otherwise speci?ed (continued) parameter test conditions temp ( o c) -8 -5 units min typ max min typ max test circuits and waveforms unless otherwise specified t a = 25 o c, v+ = +15v, v- = -15v, v ah = 4v and v al = 0.8v figure 1a. test circuit figure 1b. on resistance vs temperature figure 1c. on resistance vs analog input voltage figure 1d. on resistance vs supply voltage figure 1. on resistance 100 m a out in v in r on = v 2 100 m a v 2 hi-539 800 700 600 500 -50 temperature ( o c) on resistance ( w ) -25 0 25 50 75 100 125 v in = 0v 900 800 700 600 500 400 -12 analog input (v) on resistance ( w ) -10 -8 -6 -4 -2 0 2 4 8 10 612 125 o c 25 o c -55 o c 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 v in = 0v on resistance (k w ) 5 7 9 11 13 15 17 supply voltage ( v) hi-539
5 figure 2a. leakage current vs temperature figure 2b. i d(off) test circuit (note 6) figure 2c. i s(off) test circuit (note 6) figure 2d. i d(on) test circuit (note 6) note: 6. three measurements = 10v, 10v, and 0v. figure 2. leakage current figure 3a. supply current vs toggle frequency figure 3b. test circuit figure 3. dynamic supply current test circuits and waveforms unless otherwise specified t a = 25 o c, v+ = +15v, v- = -15v, v ah = 4v and v al = 0.8v (continued) leakage current (na) 10 1 25 temperature ( o c) 50 75 100 125 i d(on) i d(off) = i s(off) a 10v 10v 0.8v en a 0 a 1 ? similar connection for side b hi-539 ? out a i d(off) 0.8v en a ? similar connection for side b hi-539 ? a 0 a 1 10v 10v i s(off) out a out a i d(on) a 10v 10v 4v en a 0 a 1 hi-539 ? ? similar connection for side b 14 12 10 8 6 4 2 0 100hz toggle frequency i+ supply current (ma) v supply = 15v v supply = 10v functional limit 1khz 10khz 100khz 1mhz 3mhz 10mhz + 10v/ + 5v +15v/+10v v+ v- in 1a in 2a in 4a out a en 10m w 14pf a 1 a 0 50 w v a 5v gnd a -15v/-10v a -i supply +i supply -10v/-5v v a high = 4.0v low = 0v 50% duty cycle in 3a hi-539 ? ? similar connection for side b hi-539
6 figure 4a. access time vs logic level (high) figure 4b. test circuit figure 4c. measurement points figure 4d. waveforms figure 4. access time figure 5a. measurement points figure 5b. test circuit test circuits and waveforms unless otherwise specified t a = 25 o c, v+ = +15v, v- = -15v, v ah = 4v and v al = 0.8v (continued) 320 300 280 240 220 200 access time (ns) 3 logic level (high) (v) 456789101112131415 260 10v +15v v+ v- in 1a in 2a, in 4a out a en 10 50 k w pf a 1 a 0 50 w v a 5v gnd -15v 10v hi-539 in 3a 50% v ah = 4v 10% +10v 0v output -10v t a address drive (v a ) 200ns/div. s 1 on s 4 on v a input 2v/div. output 5v/div. 50% 50% v ah = 4v 0v output address drive (v a ) t open +15v v+ v- in 1a in 2, in 3a in 4a out a a 0 en a 1 12.5pf 700 v out -15v 50 w v a 5v gnd w +5v hi-539 ? ? similar connection for side b hi-539
7 figure 5c. waveforms figure 5. break-before-make delay figure 6a. measurement points figure 6b. test circuit figure 6c. waveforms figure 6. enable delays test circuits and waveforms unless otherwise specified t a = 25 o c, v+ = +15v, v- = -15v, v ah = 4v and v al = 0.8v (continued) s 1 on s 4 on v a input 2v/div. output 1v/div. 100ns/div. v ah = 4v 0v output t off(en) 50% 90% t on(en) 10% 50% enable drive (v a ) 0v +15v v+ v- in 1a in 2a thru out a a 0 en a 1 12.5pf 700 -15v v a gnd w +10v in 4a hi-539 ? ? similar connection for side b 50 w v out 100ns/div. enable drive 2v/div. enabled disabled output 2v/div. (s 1 on) hi-539
8 application information general the hl-539 accepts inputs in the range -15v to +15v, with performance guaranteed over the 10v range. at these higher levels of analog input voltage it is comparable to the hl- 509, and is plug-in compatible with that device (as well as the hl-509a). however, as mentioned earlier, the hl-539 was designed to introduce minimum error when switching low level inputs. special care is required in working with these low level signals. the main concern with signals below 100mv is that noise, offset voltage, and other aberrations can represent a large percentage error. a shielded differential signal path is essential to maintain a noise level below 50 m v rms . low level signal transmission the transmission cable carrying the transducer signal is critical in a low level system. it should be as short as practical and rigidly supported. signal conductors should be tightly twisted for minimum enclosed area to guard against pickup of electromagnetic interference, and the twisted pair should be shielded against capacitively coupled (electrostatic) interference. a braided wire shield may be satisfactory, but a lapped foil shield is better since it allows only 1 / 10 as much leakage capacitance to ground per foot. a key requirement for the transmission cable is that it presents a balanced line to sources of noise interference. this means an equal series impedance in each conductor plus an equally distributed impedance from each conductor to ground. the result should be signals equal in magnitude but opposite in phase at any transverse plane. noise will be coupled in phase to both conductors, and may be rejected as common-mode voltage by a differential amplifier connected to the multiplexer output. coaxial cable is not suitable for low level signals because the two conductors (center and shield) are unbalanced. also, ground loops are produced if the shield is grounded at both ends by standard bnc connectors. if coax must be used, carry the signal on the center conductors of two equal-length cables whose shields are terminated only at the transducer end. as a general rule, terminate (ground) the shield at one end only, preferably at the end with greatest noise interference. this is usually the transducer end for both high and low level signals. watch small d v errors printed circuit traces and short lengths of wire can add substantial error to a signal even after it has traveled hundreds of feet and arrived on a circuit board. here, the small voltage drops due to current ?ow through connections of a few milliohms must be considered, especially to meet an accuracy requirement of 12 bits or more. table 1 is a useful collection of data for calculating the effect of these short connections. (proximity to a ground plane will lower the values of inductance.) as an example, suppose the hl-539 is feeding a 12-bit converter system with an allowable error of 1 / 2 lsb ( 1.22mv). lf the interface logic draws 100ma from the 5v supply, this current will produce 1.28mv across 6 inches of #24 wire; more than the error budget. obviously, this digital current must not be routed through any portion of the analog ground return network. figure 7a. single-ended crosstalk test circuit figure 7b. differential crosstalk test circuit figure 7. crosstalk test circuits and waveforms unless otherwise specified t a = 25 o c, v+ = +15v, v- = -15v, v ah = 4v and v al = 0.8v (continued) hi-539 instrumentation amplifier ? ? ad606 or bb3630, for example + - g = 1000 350 w 1khz, 15v p-p ? ad606 or bb3630, for example hi-539 instrumentation amplifier ? + - g = 1000 350 w 1khz, 15v p-p 350 w hi-539
9 provide path for i bias the input bias current for any dc-coupled ampli?er must have an external path back to the ampli?ers power supply. no such path exists in figure 8a, and consequently the ampli?er output will remain in saturation. a single large resistor (1m w to 10m w ) from either signal line to power supply common will provide the required path, but a resistor on each line is necessary to preserve accuracy. a single pair of these bias current resistors on the hi-539 output may be used if their loading effect can be tolerated (each forms a voltage divider with r on ). otherwise, a resistor pair on each input channel of the multiplexer is required. the use of bias current resistors is acceptable only if one is con?dent that the sum of signal plus common-mode voltage will remain within the input range of the multiplexer/ampli?er combination. another solution is to simply run a third wire from the low side of the signal source, as in figure 8b. this wire assures a low common-mode voltage as well as providing the path for bias currents. making the connection near the multiplexer will save wire, but it will also unbalance the line and reduce the ampli?er's common-mode rejection. differential offset, d v os there are two major sources of d v os . that part due to the expression (r on d l d(on) +l d(on) d r on ) becomes signi?cant with increasing temperature, as shown in the electrical speci?cations tables. the other source of offset is the thermocouple effects due to dissimilar materials in the signal path. these include silicon, aluminum, tin, nickel-iron and (often) gold, just to exit the package. for the thermocouple effects in the package alone, the constraint on d v os may be stated in terms of a limit on the difference in temperature for package pins leading to any channel of the hl-539. for example, a difference of 0.13 o c produces a 5 m v offset. obviously, this d t effect can dominate the d v os parameter at any temperature unless care is taken in mounting the hl-539 package. temperature gradients across the hl-539 package should be held to a minimum in critical applications. locate the hl-539 far from heat producing components, with any air currents ?owing lengthwise across the package. table 1. wire gage equivalent width of p.c. conductor (2 oz. cu) dc resistance per foot inductance per foot impedance per foot 60hz 10khz 18 0.47 0.0064 w 0.36 m h 0.0064 w 0.0235 w 20 0.30 0.0102 w 0.37 m h 0.0102 w 0.0254 w 22 0.19 0.0161 w 0.37 m h 0.0161 w 0.0288 w 24 0.12 0.0257 w 0.40 m h 0.0257 w 0.0345 w 26 0.075 0.041 w 0.42 m h 0.041 w 0.0488 w 28 0.047 0.066 w 0.45 m h 0.066 w 0.0718 w 30 0.029 0.105 w 0.49 m h 0.105 w 0.110 w 32 0.018 0.168 w 0.53 m h 0.168 w 0.171 w hi-539
10 r on r on hi-539 v+ + - floating source v- figure 8a. r on r on hi-539 v+ + - v- power supply common power supply common 1m to 10m note: the ampli?er in figure 8a is unusable because its bias currents cannot return to the power supply. figure 8b shows two alter native paths for these bias currents: either a pair of resistors, or (better) a third wire from the low side of the signal source. figure 8b. hi-539
11 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: 92 mils x 100 mils metallization: type: alcu thickness: 16k ? 2k ? substrate potential (note): -v supply passivation: type: nitride over silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2.0k ? worst case current density: 2.54 x 10 5 a/cm 2 at 20ma transistor count: 236 process: cmos-di note: the substrate appears resistive to the -v supply terminal, therefore it may be left ?oating (insulating die mount) or it may be mounted on a conductor at -v supply potential. metallization mask layout hi-539 v- en a 0 a 1 gnd v+ outb in4b in4a outa in3a in2a in2b in1b in1a in3b hi-539

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